One or more embodiments relate to a nonvolatile memory device and a method of testing the same.
A flash memory (i.e., a nonvolatile memory) is chiefly divided into a NAND flash memory and a NOR flash memory. The NOR flash memory has an excellent random access time characteristic because it has a structure in which memory cells are independently connected to respective bit lines and respective word lines. The NAND flash memory is excellent in terms of the integration level because it has a structure in which memory cells are connected in series, requiring only one contact per cell string. Accordingly, the NAND structure is for the most part used in a high-integrated flash memory.
The above nonvolatile memory device is formed on a wafer and is configured to include a number of dies in one wafer. After the dies are tested in order to determine whether each of the dies properly operates on the wafer, only normal dies are cut and packaged. Here, one or more dies may be packaged, thereby forming one nonvolatile memory chip.
Meanwhile, a tester for testing the dies on the wafer has a predetermined number of channels. After the channels are connected to the data In-Out (IO) pins of the dies, data is inputted for a test and test results are outputted to the tester. Whether the dies normally operate can be determined based on the test results.
Since the number of channels of the tester is limited, the number of dies which can be tested at the same time depends on the number of channels connected to the dies.
FIG. 1 is a block diagram showing a known channel connection for a wafer test.
Referring to FIG. 1, the channels CH of a tester 110 are connected to dies on a wafer 120. The number of dies 121 on the wafer 120 is ‘m’ and the number of channels CH of the tester 110 is fixed. Thus, the channels CH of the tester 110 are not connected to all the m dies 121, but only n dies are connected to the channels CH of the tester 110. Here, m>n, and m and n are positive integers.
In order to test the dies 121, a program command, an address, and data to be programmed have to be inputted. To this end, the tester 110 connects the channels to the pins of each of the dies 121.
In general, each of the dies 121 includes eight IOs pins IO<7:0> for data inputs. The die 121 further includes a control signal input pin for determining whether input data is a command, an address, or data to be programmed.
In the case where the eight IOs pins IO<7:0> and the control signal input pin are connected to the respective channels of the tester 110, data is inputted for a test and the test results can be checked through the tester 110. As shown in FIG. 1, the tester 110 can test several dies at the same time in the case where the channels of the tester are connected to a number of dies.
Data IOs for a test in the case where the channels are connected to a number of the dies as shown in FIG. 1 are as follows.
FIGS. 2A and 2B are timing diagrams showing data IOs for executing a test.
FIG. 2A is a timing diagram showing a case where test data is input, and FIG. 2B is a timing diagram showing a case where test results are output.
Referring to FIG. 2A, the test data is input to each of the dies through the channels of the tester 110. Here, a clock CLK is inputted through one of the channels of the tester 110, and 8-bit data is inputted through each of the eight IOs pins int_IO<7:0> respectively connected to the remaining channels of the tester 110.
As described above, the data is inputted through each of the eight IOs pins on an 8-bit basis. For example, the data D0 of FIG. 2A is 8-bit data and can be represented by D0<7:0>.
In the case where test results are outputted, a clock CLK is input through one of the channels of the tester 110, and data is outputted through each of the eight IOs pins Out<7:0>, as shown in FIG. 2B. Here, when data is inputted, the respective IO pins are represented by int_IO<7:0> and, when data is outputted, the respective IO pins are represented by Out<7:0>.
The reason why a test is performed as described above is that, since the number of channels included in the tester 110 is limited as described above, the number of dies which can be tested at one time is also limited. If it is sought to test more dies using the same number of channels, the number of channels, connected one die, must be reduced.
To this end, a method of performing a test in the state where all channels are not connected to the eight IOs pins, but only at least four channels are connected to the eight IOs pins was developed.